1. Field of the Invention
The present invention relates to a semiconductor memory and more particularly, to a Dynamic Random Access Memory (DRAM) in which each memory cell has a stacked-capacitor structure.
2. Description of the Related Art
Recently, to increase the number of memory cells placed on a semiconductor chip of a DRAM, the occupied area of each memory cell has been required to be reduced to make its capacity larger. If the storage capacitor of each memory cell is made smaller, the occupied area can be reduced, however, in the case, the capacitor has to had a sufficient capacitance for exactly reading out the storage data value in the cell. Accordingly, as a technique to enable the storage capacitance larger without increasing its memory cell area, the stacked-capacitor structure has been developed and employed. A conventional DRAM with the stacked-capacitor memory cells is disclosed, for example, in the Japanese Non-examined Patent Publication 2-86164.
A sample of a conventional DRAM memory cell of this sort is illustrated in FIG. 1, in which a patterned field oxide 42 is formed on a surface of a p-type silicon substrate 41 to make an active device area on its surface area. In the active device area, a pair of source/drain regions 45a and 45b of a metal-oxide-semiconductor (MOS) transistor are formed in the substrate 41, and a polysilicon gate electrode 44 is formed through a gate oxide 43 on the substrate 41. The pair of source/drain regions 45a and 45b are made of n-type diffusion regions, respectively. The gate electrode 44 acts as a part of one of word lines.
The exposed surfaces of the field oxide 42, the gate electrode 44 and the substrate 41 are covered with a first interlayer insulator 46. With the active device area, one of bit lines 47, which are formed on the first interlayer insulator 46 and made of refractory metal-silicide, is contacted through a contact hole of the first interlayer insulator 46 with the source/drain region 45a at a contact area 56.
A second interlayer insulator 48 is formed on the first interlayer insulator 46 with covering the bit lines 47. The polysilicon storage electrode 51 is formed on the second interlayer insulator 48. The storage electrode 51 is contacted through a contact hole penetrating the first and second interlayer insulator 46 and 48 with the source/drain region 45b at a contact area 57.
A dielectric 52, which is made of a silicon dioxide (SiO.sub.2) film and a silicon nitride (Si.sub.3 N.sub.4) film, is formed on the storage electrode 51 along the surface of the electrode 51, thus the entire surface of the electrode 51 is covered with the dielectric 52. The surface of the dielectric 52 and the exposed surface of the second interlayer insulator 48 are covered with a polysilicon opposite electrode 53. The polysilicon storage electrode 51, the opposite electrode 53 and the dielectric 52 constitutes a storage capacitor.
A third interlayer insulator 50 is formed on the capacitor opposite electrode 53 so as to cover the entire surface of the electrode 53, and on the third interlayer insulator 50, a wiring line 49 made of aluminum system metal is formed. The wiring line 49 constitutes a part of one of word lines together with the gate electrode 44.
In the above-described DRAM memory cell, to reduce the cell area and to ensure sufficient capacitance of the storage capacitor for normal operation, the thickness of the storage electrode 51 is required to be increased thereby to enlarge its surface area, or any material with a larger dielectric constant .epsilon. such as tantalum oxide (Ta.sub.2 O.sub.5), lead zirconate titanate (PZT) or the like is required to be employed as the dielectric 52.
However, if the thickness of the storage electrode 51 is increased, there arises the following problem: Since there arises a large difference in level between the memory cell area containing the storage capacitor and a peripheral circuit area of the DRAM, their optimum focal points become badly different from each other in the process of forming the wiring lines 49 by photolithography and etching techniques. If the difference in level is beyond the given focusing margins of the stepping projection aligner or stepper and the photoresist film used in the process, the configuration or shape of the photoresist film after patterning deteriorates and as a result, disconnection and/or short-circuit in the wiring lines 49 becomes easy to occur.
In addition, when metal oxide is used as the dielectric 52, the process temperature has to be kept at or under a given temperature such as 600.degree. C. during the process for forming the storage capacitor and subsequent processes in order to prevent the dielectric constant reduction of the metal oxide due to a chemical reaction between the metal oxide and the storage electrode material and/or oxidation of the storage electrode material. However, with the conventional memory cell, in order to facilitate formation of the wiring lines 49, the second interlayer insulator 48 made of boron-doped phosphosilicate glass (BPSG) is deposited on the first interlayer insulator 46 and thereafter, its heat treatment is required to be carried out at a high temperature such as 800.degree. to 900.degree. C. to reflow the BPSG film 48 for its planarization. Therefore, there is another problem that it is difficult to employ metal oxide as the dielectric 52.